Charis Poag, 1/5/13
The following information was
obtained for a company I am applying for (omitted name). One of the Design directors asked me some
questions during the interview. So I went ahead and did some research to
refresh my mind on their technologies over the weekend.
Power i nformation came from: http://users.ece.utexas.edu/~kwasinski/teaching.html
and some from Wikipedia and youtube videos.
Main knowledge of DSP information came from: http://users.ece.utexas.edu/~bevans/courses/realtime/lectures/index.html
a) Buck converters-
A buck converter is a method to "step-down DC to DC
converter". Our goal is to have a
high efficiency design, ie our lossless objective: Power in = power out, thus Vin*Iin
=Vout*Iout -> Vout/Vin = Iin/Iout. The typical buck converter design is
shown in the figure below.
Note: the switch is typically a MOSFET,IGBT, or BJT.
Idea: voltage regulation by the inductor--
Also energy stored in an inductor is described as-
The theory of operation is fairly simple, with an inductor and two
switches (usually created with a transistor and a diode) which controls the
inductor converter. The best way to understand this is to think in terms of the
inductor's reluctance to allow a change in current. So when the switch is open
(seen in picture below as the "off" position), the current in the
circuit is 0 in the beginning. But when the switch is closed, the current
begins to increase, but the inductor does not want it to change from 0, so it
attempts to fight the increase by dropping the voltage. The voltage drop
counters the voltage of the source and reduces the net voltage across the load.
Over time, the inductor allows current to increase slowly by decreasing the voltage it drops, thus
increasing the net voltage seen by the load. This process causes the inductor
to store the energy in the form of a magnetic field.
If the switch is opened before the inductor fully charges (in other
words, before it has allowed all current to pass through by reducing its own
voltage drop to 0), then there will always be a voltage drop across it. Thus
the net voltage seen by the load is always less than the input voltage source.
Overtime, the inductor allows the current to decrease gradually, which it does
by decreasing the voltage across itself. During this time, the inductor is
discharging its stored energy into the rest of the circuit.
If the switch is closed again before the inductor fully discharges, the
load will always see a non-zero voltage. The capacitor placed in parallel with
the lad helps smooth out this voltage waveform as the inductor charges and
discharges each cycle. As seen in the figure below the circuit diagrams.
By keeping the inductor in a state of not fully charging and
discharging we are able to create a circuit which lowers the output voltage.
This also allows us to control the power efficiency of the circuit. A more in
depth discussion of this circuit can be found on Wikipedia or other educational
resources which describe the continuous and discontinuous modes of the
inductors cycles and control of the current seen across the load. For example
in continuous mode if you can find out what duty cycle you need to step down 12v to 3v. In that particular case
you need a 25% duty cycle in our theoretical ideal circuit.
This is due to D (uty cycle) =Vout/Vin =0.25 duty cycle.
b) Boost converters-
Note: the switch is typically a MOSFET,IGBT, or BJT.
Idea: voltage regulation by the inductor--
Also energy stored in an inductor is described as-
The circuit above is used to take a DC voltage and raise it to a higher
DC voltage. The DC-to-DC power converter uses switched-mode power supply (SMPS)
containing at least two semiconductor switches (a diode and a transistor) with
at least one energy storage element, a capacitor, inductor or the two in
combination. Filters made of capacitors(sometimes in combination with
inductors) are normally added to the output of the converter to reduce output
voltage ripple.
This is also called a "step
up converter" because it steps up the voltage source. Since power must be
conserved (P=VI), the output current is lower than the source current. And as
mentioned in the Buck converter, we use
the inductors capability to control the voltage, due to the rate of change of
current across itself. Boost converters are often used for DC sources such as
batteries, solar panels, rectifiers and DC generators.
The circuit analysis is quite similar to the buck converter. As
mentioned in that section, we use the inductor to resist changes in current,
thus controlling the voltage. In a boost converter, the output voltage is always
higher than the input voltage.
The basic principle of the boost converter consists of two distinct
states as see above:
1) The on state: the switch is closed, resulting in an increase of
inductor current
2) The off state: the switch is open and the only path offered to the
inductor current is through the flyback diode, the capacitor C and the load R. This
results in transferring energy accumulated during the on state into the
capacitor connected in parallel with the load.
To find out what duty cycle you need to say convert 12v to 24v then use the duty cycle conversion equation. D = 1-(12/24) = 1-0.5 = 0.5.
c) PWM-
Used for controlling power to inertial electrical devices, made
practical my modern power switches. Longer the switch is on compared to off
periods, the higher the power supplied to load is. PWM is use for several
electronic application, including: telecommunications signal modulation, power delivery to a load, voltage regulation,
and audio effects/amplification. An
example of how PWM is used to convert digital signal to an analog signal is
shown below.
Above is an example to control speed of a motor. Lets say the duty cycle = time on/time off = 0.5 voltage swings from 0 to 12 volts. Then average voltage = 0.5 * 12v = 6volt average being supplied to the motor.
**Also used for Digital to Analog converter.
From my experience , an easy way of creating a duty cycle could be done
by using a microcontroller which you can turn off and on an output voltage that
is controlled with a timing interrupt. A
wonderful reference for a PWM driver can be found on my professor Valvano's
website (http://users.ece.utexas.edu/~valvano/EE345L/Lectures/LLec27_PWMmotor.pdf)
Example code of a timer to create PWM on an ARM processor can be found below.
Here are some examples of duty cycles:
// Timer0APWM.c
// Runs on LM3S811
// Use Timer0A in PWM mode to generate
a square wave of a given
// period with 50% duty cycle.
// Daniel Valvano
// June 27, 2011
/* This example accompanies the book
"Embedded Systems: Real Time Interfacing to the Arm Cortex
M3",
ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2011
Copyright 2011 by Jonathan W. Valvano,
valvano@mail.utexas.edu
You may use, edit, run or distribute this file
as long as the above copyright notice remains
THIS SOFTWARE IS PROVIDED "AS
IS". NO WARRANTIES, WHETHER
EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO,
IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE APPLY TO THIS SOFTWARE.
VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE
LIABLE FOR SPECIAL, INCIDENTAL,
OR CONSEQUENTIAL DAMAGES, FOR ANY REASON
WHATSOEVER.
For more information about my classes, my
research, and my books, see
http://users.ece.utexas.edu/~valvano/
*/
#define TIMER0_CFG_R (*((volatile
unsigned long
*)0x40030000))
#define TIMER0_TAMR_R (*((volatile
unsigned long
*)0x40030004))
#define TIMER0_CTL_R (*((volatile
unsigned long
*)0x4003000C))
#define TIMER0_TAILR_R (*((volatile
unsigned long
*)0x40030028))
#define TIMER0_TAMATCHR_R (*((volatile
unsigned long
*)0x40030030))
#define TIMER0_TAMATCHR_R (*((volatile
unsigned long
*)0x40030030))
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer
configuration,
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA
Alternate Mode
// Select
#define TIMER_TAMR_TAMR_PERIOD 0x00000002
// Periodic Timer mode
#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA
Enable
#define TIMER_TAILR_TAILRL_M 0x0000FFFF
// GPTM TimerA Interval Load
// Register Low
#define TIMER_TBILR_TBILRL_M 0x0000FFFF
// GPTM TimerB Interval Load
// Register
#define GPIO_PORTD_AFSEL_R (*((volatile
unsigned long
*)0x40007420))
#define GPIO_PORTD_DEN_R (*((volatile
unsigned long
*)0x4000751C))
#define SYSCTL_RCGC1_R (*((volatile
unsigned long
*)0x400FE104))
#define SYSCTL_RCGC2_R (*((volatile
unsigned long
*)0x400FE108))
#define SYSCTL_RCGC1_TIMER0 0x00010000
// timer 0 Clock Gating Control
#define SYSCTL_RCGC2_GPIOD 0x00000008 // port D Clock
Gating Control
void WaitForInterrupt(void); // low power mode
// period is number of clock cycles in
PWM period ((1/clock) units)
void PWOut_Init1(unsigned short period){
volatile unsigned long delay;
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0;//
activate timer0
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; //
activate port D
delay =
SYSCTL_RCGC2_R; // allow time to finish activating
GPIO_PORTD_DEN_R |= 0x10; // enable digital I/O on PD4
GPIO_PORTD_AFSEL_R |= 0x10; // enable alt funct on PD4
TIMER0_CTL_R &= ~TIMER_CTL_TAEN; //
disable timer0A during setup
TIMER0_CFG_R = TIMER_CFG_16_BIT; // configure
for 16-bit timer mode
// configure for alternate (PWM) mode
TIMER0_TAMR_R = (TIMER_TAMR_TAAMS|TIMER_TAMR_TAMR_PERIOD);
TIMER0_TAILR_R = period-1; // timer start value
//
TIMER0_TAMATCHR_R = period/4;
// duty cycle = 75%
TIMER0_TAMATCHR_R = period/2; // duty cycle = 50%
//
TIMER0_TAMATCHR_R = 3*period/4;
// duty cycle = 25%
TIMER0_CTL_R |= TIMER_CTL_TAEN; // enable timer0A 16-b, PWM, 50% duty
}
//debug code
int main(void){
//
PWOut_Init1(300); // initialize timer0A in PWM mode
(20,000 Hz)
//
PWOut_Init1(1200);
// initialize timer0A in PWM mode (5,000 Hz)
PWOut_Init1(6000); // initialize timer0A in PWM mode (1,000 Hz)
while(1){
WaitForInterrupt();
}
}
d) LDO-
For the circuit above (LDO) the output voltage is defined as
Primarily, the main components for an LDO circuit consists of a power
FET and a differential amplifier (error amplifier). One input of the
differential amplifier monitors the fraction of the output determined by the
resistor ratio of R1 and R2. The second input to the differential amplifier is
from a stable voltage reference (bandgap reference). If the output voltage
rises too high relative to the reference voltage, the drive to the power FET
changes to maintain a constant output voltage.
These LDO regulators work in the same way as all linear voltage
regulators, however the main difference is their schematic topology. Instead of
an emitter follower topology (shown below, low-dropout regulators use open
collector or open drain topology. This allows transistor saturation, which
allows the voltage drop from the unregulated voltage to the regulated voltage
to be as low as the saturation voltage across the transistor.
Just for my reference, I added a quick discussion of
transistors. The transistor allows it to function as an amplifier or switch.
This is accomplished by using a small amount of electricity to control a gate
on which larger supply of electricity. The transistor's supply of voltage is
comparable to turning a valve to control a supply of water.
Transistors have 3 parts: base, collector, and emitter. The
base is the gate controller for the device for larger electrical supply the
emitter is the outlet for the supply. The collector is the larger electrical
supply, and the emitter is the outlet for that supply. By sending varying
levels of current from the base, the amount of current flowing through the gate
from the collector can be regulated. In this way, a very small amount of
current may be used to control a large amount of current, for example within an
amplifier. The same process is used to create binary code for digital
processors, but in this case a voltage threshold of 5 volts is needed to open
the collector gate. This process allows the transistor to be used as a switch
with binary function of - 5 volts = on and less than 5 volts = off.
e) Advantages of FIR vs IIR
filters
A wealth of information on FIR filters can be found here: http://www.eas.uccs.edu/wickert/ece2610/lecture_notes/ece2610_chap5.pdf
A wealth of information on IIR filters can be found here:
Quick notes about the above information:
- x[n] is the input signal,
- y[n] is the output signal,
- are the filter coefficients, also known as tap weights, that make up the impulse response,
- is the filter order; an th-order filter has (N+1) terms on the right-hand side. The x[n-i] in these terms are commonly referred to as taps, based on the structure of a tapped delay line that in many implementations or block diagrams provides the delayed inputs to the multiplication operations. One may speak of a 5th order/6-tap filter, for instance
FIR- current input depends on pas and previous input samples as well as
previous output samples.
IIR (feedback)- y[n] =
b0x[n]+b1x[n-1]+...+bmx[n-m] - a1y[n-1]-a2y[n-2]-any[n-N]
|
FIR- y[n] = b0x[n]+b1x[n-1]+...+bmx[n-N]
= sum from i= 0 to N (bi * x[n-i])
|
|
stability
|
Can be unstable, can have limit cycles
|
Liner phase always possible, no limit cycles
|
Order
|
less
|
more
|
History
|
Derived from analog filters
|
No analog history
|
other
|
Polyphase implementation possible can always be made causal.
|
|
Use less memory and calculations than similar FIR filters
|
More memory
|
|
Recursive implementations (short order)
|
Too long and may cause various application problems (long order)
|
IIR filters are difficult to control and have no particular phase, where as FIR
filters make linear phase always possible. IRR can be unstable, whereas FIR is
always stable. IIR, when compared to FIR, can have limited cycles, but FIR has
no limited cycles. IIR is derived from analog, where as FIR has no analog
history. IIR can make polyphase implementation possible, whereas FIR can be
made casual (linear time-invariant system; depends only on past and present
inputs, not future).
