Sound 101

So today I wanted to purchase new head phones. Just when I got back I was just wanting to confirm the specifications that I used to purchase. Which by the way, I purchased the JVC HA-S600-B from Fry's. 

I specifically liked the frequency range of the sound - 8Hz-25KHz. So it had a nice range of bass as well as treble.

Here is a cool website that explained everything that goes on behind sound engineering. - http://www.tech-forums.net/forums/f12/sound-101-a-169733/
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So... you're lookin fer some bumpin speakers eh? Well, heres some tips for you. Headphones can also follow these guidelines!

First of all, wattage isn't everything. Wattage is only the power your feeding to it. Also, especially when looking at 5.1 or 7.1 systems, when the box says "A WHOPPING 100w!", you have to remember... that 100watts is divided 6 ways (5.1) or even 8 ways (7.1). Usually, the sub will get most of the power and the satellites will get a miniscule amount. Higher wattage is good, but not always better. As this is just basic information, I'm not going to get into RMS and Peak power ratings, but researching these two forms of power is DEFINITELY a must when looking at speakers/amps. Also, resistance (ohms) is another thing you may want to dabble into.

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Since wattage isn't everything, what is? Sensitivity!!! Ok... so you spent your hard earned cash on some awesome speakers with 500 watts of power. Freakin sweet eh? You open the box, get everything all set up and you go to press PLAY anxiously waiting for your heart to be resuscitated by the massive 500watts flowing through them speakers. You press play and what you hear is good. Then you take the dive and turn the volume up. "WTF?! I've got these things all the way up and they aren't loud whatsoever!! WHAT BS!!!" Sensitivity my good friend. So what is sensitivity? Well, in most specifications you will see a section called Signal to noise ratio (SNR) or sensitivity. Then you will get a number followed by dB (decibels). Say this number is 50dB (which is horrendous), that means for every one watt of power going in, 50 decibels of sound will come out (if playing white noise at nominal level). Most consumer quality stuff ranges from 70-80's. You really want at least 89dB. Anything above 90 will give you plenty of volume and will use its wattage more efficiently.

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Anything else? DUH! We haven't even scratched the surface! Frequency range!! Frequency range is that weird section of numbers that no one ever understands. (100-20,000hz). What the heck does that mean? Well, hz (hertz) is a measurement of how many times a sound wave cycles in one second. So, the lower the number, the slower the wave. Thusly, the slower the wave, the lower it sounds. The human hearing range is technically 20hz-20,000hz (or 20khz). I consider the USABLE range to be 30hz-18khz Although I can hear 20-20k, people above 25 years old(ranges) can't hear much above 17k due to hearing damage (no matter what you do, it happens when you get older).

A GOOD frequency range is having the first number as low as possible and the second number as high as possible. So, if your speakers have a 75hz-16,000hz (which is not so great) range, if you play anything below or above those numbers, you wont hear it as your speakers can't play it. Chest thumping is normally found around 30-60hz. A good range I like to follow is to keep the first number below 50hz and the high number at least at 18khz (or 18,000hz).

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Digital versus analog! WHAT?! THERE ARE NO SUCH THINGS AS DIGITAL SPEAKERS! NEVER! Speakers are purely an analog mechanism. A speaker consists of a magnet, a voice coil, a spider and a cone (with a dust cap in the middle, which really serves no purpose). Essentially, the speaker vibrates (in AND out) to move molecules which form sound waves. When a description says DIGITAL SPEAKERS, that means it has a digital to analog converter (AD/DA) OR it has a digital decoder built in. Digital connections only transmit information. No audio whatsoever. Just a bunch of ones and zeros.

So now you should have a basic understanding about speakers and headphones. Now, go out and get yourself some GOOD speakers (excluding Bose).

Whats next? Wiring!

Let's say you've got some sweet speakers and a really sweet amp. Rock on eh? Car install, home theater, whatever... wiring it all up goes here! There are a few different ways to wire things up, but first we gotta understand the basics:

• Ohms (impedence or resistance)
• Wattage
• Load
• Phase

Let's start with resistance! This can be quite the challenge, but its quite simple. Every speaker has a level of resistance, called impedence. Impedence is measured in what's called Ohm's. Now, we could get crazy and go into Ohm's Law, but theres really no point without going into some advanced stuff. Just so you can see it, here is the Ohm's Law chart:



This is used for figuring Impedence (resistance), wattage, voltage, and current. Simple math as long as you know the information. Anyways, back to resistance. You know how on your amplifier it says it can handle X amount of ohms? Well, thats what is called Load. 8ohms and 4ohms are the most common, but there are components that run even lower than that. How do we figure out load? Well, that all depends on how things are wired up. There are three ways to wire: Series, Parallel, and Series Parallel (I know, scary... don't worry). When hooking up more than one speaker, you have to use one of these wiring methods. Though it may seem obvious, but "black goes to black and red goes to red". These are the positive and negative leads. This gets into phase, which we'll learn a bit later.

Series:



As you can see, there are two 8ohm speakers hooked up. When you wire them in series method, you add the resistance of all of the speakers, and you get your load. In this case, 8+8= 16ohm load. REMEMBER! The higher the resistance, the lower the output. Why? Most amplifiers can handle high loads. The less resistance there is, the more power the speakers will draw from the amp, the more output (and we all know what that means... LOUDER!). The smaller load rating on the amp, the better. If the amp can handle 2 ohms, you better be sure it can give you more than enough power for any application. In the case of the picture above, it won't be very hard at all for the amp to drive those two speakers, but keep in mind that it sure isn't going to get that loud. It may be better to wire it in a different method, such as parallel!


Parallel:



Here we have the same to speakers, but wired differently. When wiring in parallel, you multiply the resistance of all of the speakers, and divide it by the sum of all the resistance of the speakers. This will give you your load rating. Here we have two 8ohm speakers wired in parallel. So, we take 8 * 8 = 64 ---- 64 / 16 = 4 ---- This gives us a load of 4ohms. If we were to hook up this to the same amplifier as we did with series, we would get a much high output since it is drawing much more power from the amp.

Series Parallel

Embedded Systems Interview Review

Today, I have a few interviews lined up. I want to do well of course, so I thought I would lay out some interview review.

Let's begin!

A really awesome review is linked here- http://www.sanjayahuja.com/Interview%20questions.pdf
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This information came from- http://careerride.com/embedded-systems-interview-questions.aspx

What is the need for an infinite loop in Embedded systems?

Infinite Loops are those program constructs where in there is no break statement so as to get out of the loop, it just keeps looping over the statements within the block defined.
Example:
While(1) {}

OR

for(;;);
{
//Code
}
Embedded systems need infinite loops for repeatedly processing/monitoring the state of the program. One example could be the case of a program state continuously being checked for any exceptional errors that might just occur during run time such as memory outage or divide by zero etc.,

For e.g. Customer care Telephone systems where in a per-recorded audio file is played in case the dialer is put on hold..

Also circuits being responsible for indicating that a particular component is active/alive during its operation by means of LED's.

How does combination of functions reduce memory requirements in embedded systems?

The amount of code that has to be dealt with is reduced thus easing the overhead and redundancy is eliminated in case if there is anything common among the functions.

Memory allocation is another aspect that is optimized and it also makes sense to group a set of functions related in some way as one single unit rather than having them to be dispersed in the whole program.

In case of interactive systems display of menu list and reading in the choices of user's could be encapsulated as a single unit.

A vast majority of High Performance Embedded systems today use RISC architecture why?

According to the instruction sets used, computers are normally classified into RISC and CISC. RISC stands for 'Reduced Instruction Set Computing' .The design philosophy of RISC architecture is such that only one instruction is performed on each machine cycle thus taking very less time and speeding up when compared to their CISC counterparts.

Here the use of registers is optimized as most of the memory access operations are limited to store and load operations.

Fewer and simple addressing modes, and simple instruction formats leads to greater efficiency, optimization of compilers, re-organisation of code for better throughput in terms of space and time complexities. All these features make it the choice of architecture in majority of the Embedded systems.

CISC again have their own advantages and they are preferred whenever the performance and compiler simplification are the issues to be taken care of.

CISC	RISC
Emphasis on hardware	Emphasis on software
Includes multi-clock complex instructions	Single-clock, reduced instruction only
Memory-to-memory: "LOAD" and "STORE" incorporated in instructions	Register to register: "LOAD" and "STORE" are independent instructions
Small code sizes, high cycles per second	Low cycles per second, large code sizes
Transistors used for storing complex instructions	Spends more transistors on memory registers

However, the RISC strategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room



The Performance Equation
The following equation is commonly used for expressing a computer's performance ability:

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. 

 

 (above table- http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/)

Why do we need virtual device drivers when we have physical device drivers?

Device drivers are basically a set of modules/routines so as to handle a device for which a direct way of communication is not possible through the user's application program and these can be thought of as an interface thus keeping the system small providing for minimalistic of additions of code, if any.
Physical device drivers can’t perform all the logical operations needed in a system in cases like IPC, Signals and so on...
The main reason for having virtual device drivers is to mimic the behaviour of certain hardware devices without it actually being present and these could be attributed to the high cost of the devices or the unavailability of such devices.
These basically create an illusion for the users as if they are using the actual hardware and enable them to carryout their simulation results.
Examples could be the use of virtual drivers in case of Network simulators,also the support of virtual device drivers in case a user runs an additional OS in a virtual box kind of a software.

What is the need for DMAC in ES?

Direct memory access is mainly used to overcome the disadvantages of interrupt and progam controlled I/O.
DMA modules usually take the control over from the processor and perform the memory operations and this is mainly because to counteract the mismatch in the processing speeds of I/O units and the procesor.This is comparatively faster.

It is an important part of any embedded systems,and the reason for their use is that they can be used for bursty data transfers instead of single byte approaches.
It has to wait for the systems resources such as the system bus in case it is already in control of it.

What is Endianness of a system and how do different systems communicate with each other?

Endianness basically refers to the ordering of the bytes within words or larger bytes of data treated as a single entity.
When we consider a several bytes of data say for instance 4 bytes of data,XYZQ the lower byte if stored in a Higher address and others in successively decreasing addresses ,then it refers to the Big Endian and the vice versa of this refers to Little Endian architecture.
Intel 80x86 usually follows Little Endian and others like IBM systems follow Big Endian formats.
If the data is being transmitted care has to be taken so as to know as to which byte,whether the higher or the lower byte is being transmitted.
Hence a common format prior to communication has to be agreed upon to avoid wrong interpretation/calculations.
Usually layer modules are written so as to automate these conversion in Operating systems.


"Little Endian" means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (The little end comes first.) For example, a 4 byte LongInt

    Byte3 Byte2 Byte1 Byte0

will be arranged in memory as follows:

    Base Address+0   Byte0
    Base Address+1   Byte1
    Base Address+2   Byte2
    Base Address+3   Byte3

Intel processors (those used in PC's) use "Little Endian" byte order. "Big Endian" means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. (The big end comes first.) Our LongInt, would then be stored as:

    Base Address+0   Byte3
    Base Address+1   Byte2
    Base Address+2   Byte1
    Base Address+3   Byte0

Motorola processors (those used in Mac's) use "Big Endian" byte order.
^Found from http://people.cs.umass.edu/~verts/cs32/endian.html

How are macros different from inline functions?

Macros are normally used whenever a set of instructions/tasks have to be repeatedly performed. They are small programs to carryout some predefined actions.
We normally use the #define directive in case we need to define the values of some constants so in case a change is needed only the value can be changed and is reflected throughout.
#define mul(a,b) (a*b)
The major disadvantage of macros is that they are not really functions and the usual error checking and stepping through of the code does not occur.
Inline functions are expanded whenever it is invoked rather than the control going to the place where the function is defined and avoids all the activities such as saving the return address when a jump is performed. Saves time in case of short codes.
inline float add(float a,float b)
{
return a+b;
}
Inline is just a request to the compiler and it is upto to the compiler whether to substitute the code at the place of invocation or perform a jump based on its performance algorithms.

What could be the reasons for a System to have gone blank and how would you Debug it?

Possible reasons could be,
- PC being overheated.
- Dust having being accumulated all around.
- CPU fans not working properly .
- Faulty power connections.
- Faulty circuit board from where the power is being drawn.
- Support Drivers not having being installed.

Debugging steps which can be taken are:

- Cleaning the system thoroughly and maintaining it in a dust-free environment.
Environment that is cool enough and facilitates for easy passage of air should be ideal enough.

- By locating the appropriate support drivers for the system in consideration and having them installed.

Explain interrupt latency and how can we decrease it?

Interrupt latency basically refers to the time span an interrupt is generated and it being serviced by an appropriate routine defined.,usually the interrupt handler.
External signals,some condition in the program or by the occurrence of some event,these could be the reasons for generation of an interrupt.
Interrupts can also be masked so as to ignore them even if an event occurs for which a routine has to be executed.
Following steps could be followed to reduce the latency
- isrs being simple and short.
- Interrupts being serviced immediately
- Avoiding those instructions that increase the latency period.
- Also by prioritizing interrupts over threads.
- Avoiding use of inappropriate APIs.

How to create a child process in linux?

Prototype of the function used to create a child process is pid_t fork(void);
Fork is the system call that is used to create a child process. It takes no arguments and returns a value of type pid_t.
If the function succeeds it returns the pid of the child process created to its parent and child receives a zero value indicating its successful creation.
On failure, a -1 will be returned in the parent's context, no child process will be created, and errno will be set
The child process normally performs all its operations in its parents context but each process independently of one another and also inherits some of the important attributes from it such as UID, current directory, root directory and so on.

Significance of watchdog timer in Embedded Systems

Watchdog timer is basically a timing device that is set for predefined time interval and some event should occur during that time interval else the device generates a time out signal.
One application where it is most widely used is when the mobile phone hangs and no activity takes place,in those cases watchdog timer performs a restart of the system and comes to the rescue of the users.
It is used to reset to the original state whenever some inappropriate events take place such as too many commands being given at the same time or other activities that result in malfunctioning of the GUI.It is usually operated by counter devices.

If you buy some RTOS, what are the features you look for in ?

-Deterministic operating system having guaranteed worst-case interrupt latency and context-switch times.
-Documentation providing for the minimum, average, and maximum number of clock cycles required by each system call
-Interrupt response times should be very minute.
-Context switch time should be very low.
-Compatibility with several plugin devices.
- Overall it should be very reliable.

Why is java mostly used in embedded systems?

Java was mainly designed and conceputalised for code that can work on different platforms without any hassles and also for being secure enough so as to not harm or corrupt other modules of code.
Features like exception handling,simple syntax and Automatic Garbage collection all work in its favour as the language for use in ES's.
Also that it is widely used in the form of Java applets makes it very popular confining it to the limits of JVM.It is Dynamic in nature.
Its use is also being exploited in enterprise systems in the form of J2EE ,J2SE
J2ME in case of mobile applications.

Differentiate between mutexes vs semaphores

-Semaphores is a synchronisation tool to overcome the critical section problem.
- A semaphore S is basically an integer variable that apart from initialisation is accesses only through atomic operations such as wait() and signal().
- Semaphore object basically acts as a counter to monitor the number of threads accessing a resource.
- Mutex is also a tool that is used to provide deadlock free mutual exclusion.It protects access to every critical data item.if the data is locked and is in use,it either waits for the thread to finish or awakened to release the lock from its inactive state.

What are the commonly found errors in Embedded Systems?

- Damage of memory devices due to transient current and static discharges.
- Malfunctioning of address lines due to a short in the circuit
- Malfunctioning of Data lines.
- Some memory locations being inaccessible in storage due to garbage or errors.
- Improper insertion of Memory devices into the memory slots
- Faulty control signals.

What is the need for having multibyte data input and output buffers in case of device ports?

It’s normally the case that some devices transfer the output either in a bursty or a sequential manner and also during input entry. If we take the example of keyboards, all the data entered is stored in a buffer and given at a time or one character at a time.
In case of networking there may be several requests to access the same resource and all these are queued in a buffer and serviced in the order they are received
Hence to avoid the input/output units from getting overloaded with requests, we use multibyte buffers.

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The following are basic interview questions for embedded systems - found http://careerride.com/embedded-systems-interview-for-freshers.aspx

What is lst file?

• This file is also called as list file.
• It lists the opcodes ,addresses and errors detected by the assembler.
• List file is produced only when indicated by the user.
• It can be accessed by an editor and displayedon monitor screen or printed.
• Progammer uses this file to find the syntax errors and later fix them.

How is a program executed’ bit by bit’ or’ byte by byte’?

EXAMPLE

ADDRESS	OPCODE	PROGRAM
1   0000		ORG 0H
2   0000	7D25	MOV R5,#25H
3   0002	7F34	MOV R7,#34H
4   0004	2D	ADD A, R5
5   0005		END

• A program is always executed byte by byte.
• Firstly,1st opcode 7D is fetched from location 0000 and then the value 25 is fetched from 0001 .
• 25 is then placed in the register R5 and program counter is incremented to point 0002.
• On execution of opcode 7F, value 34 is copied to register R7.
• Then addition of contents of R5 and accumulater takes place.
• Here all the opcodes are 8 bit forming a byte.

Explain DB.

• DB is called as define byte used as a directive in the assembler.
• It is used to define the 8 bit data in binary ,hexadecimal or decimal formats.
• It is the only directive that can be used to define ASCII strings larger than two characters.
• DB is also used to allocate memory in byte sized chunks.
• The assembler always converts the numbers lnto hexadecimal.

What is EQU?

• EQU is the equate assmbler directive used to define a constant without occupying a memory location.
• It associates a constant value with data label .
• Whenever the label appears in the program ,constant value is subsituted for label.
• Advantage: The constant value occuring at various positions in a program can be changed at once using this directive.
• Syntax: label EQU constant value

How are labels named in assembly language?

• Label name should be unique and must contain alphabetic letters in both uppercase and lowercase.
• 1st letter should always be an alphabetic letter.
• It can also use digits and special characters ?,.,@,_,$.
• Label should not be one of the reserved words in assembly language.
• These labels make the progam much easier to read and maintain.

Are all the bits of flag register used in 8051?

• The flag register also called as the program status word uses only 6 bits.
• The two unused bits are user defineable flags.
• Carry ,auxillary carry ,parity and overflow flags are the conditional flags used in it.
• PSW.1 is a user definable bit and PSW.5 can be used as general purpose bit.
• Rest all flags indicate some or the other condition of an arithematic operation.

Which bit of the flag register is set when output overflows to the sign bit?

• The 2nd bit of the flag register is set when output flows to the sign bit.
• This flag is also called as the overflow flag.
• Here the output of the signed number operation is too large to be accomodated in 7 bits.
• For signed numbers the MSB is used to indicate the whether the number is positive or negative.
• It is only used to detect errors in signed number operations. 

Which register bank is used if we use the following instructions
SETB  PSW.3      A
SETB  PSW.4       B

• Statement A sets 3rd bit of flag register.
• Statement B sets 4th bit of flag register.
• Therefore register bank 3 is initiated .
• It uses memory location 18H to 1FH.
• The register bank is also called as R3.

Issues related to stack and bank 1.

• Bank 1 uses the same RAM space as the stack.
• Stack pointer is incremented or decremented according to the push or pop instruction.
• If the stack pointer is decremented it uses locations 7,6,5… which belongs to register bank 0.
• If a given program uses R1 then stack is provided new memory location.
• The push instruction may also take stack to location 0 i.e.it will run out of space.

Explain JNC.

• It is a command used to jump if no carry occurs after an arithematic operation.
• It is called as jump if no carry( conditional jump instruction).
• Here the carry flag bit in PSW register is used to make decision.
• The processor looks at the carry flag to see if it is raised or not.
• If carry flag is 0 ,CPU fetches instructions from the address of the label.

Write a program to toggle all bits of P1 every 200ms.

                    MOV              A,#55H
AGAIN:       MOV              P1,A
                    ACALL          DELAY
                    CPL               A
                    SJMP            AGAIN

DELAY:
                    MOV              R5,#9
HERE1:     MOV              R4,#242
HERE2:     MOV              R3,#255
HERE3:     DJNZ            R3,HERE3
                    DJNZ            R4,HERE2
                    DJNZ            R5,HERE1
                    RET
• Here the delay produced is 9*255*4MC*90=199,940 micro seconds.
• CPL is used to toggle the bits of P1.
• Short jump is jusd to produce a continuous loop.

Can port 0 be used as input output port?

• Yes, port 0 can be used as input output port.
• Port 0 is an open drain unlike ports 2,3,4.
• To use it as input or output the 10k ohm pull-up resisters are connected to it externally.
• To make port 0 as input port it must be programmed by writing 1 to all bits.
• Example:

MOV  A,#0FFH
MOV  P0,A

Which 2 ports combine to form the 16 bit address for external memory access?

• Port0 and port2 together form the 16 bit address for external memory.
• Port0 uses pins 32 to 39 of 8051 to give the lower address bits(AD0-AD7)
• Port2 uses pins 21 to 28 of 8051 to give the higher address bits(A8-A15)
• This 16 bit address is used to access external memory if attached.
• When connected to external memory they cannot be used as input output ports.

Can single bit of a port be accessed in 8051?

• Yes,8051 has the capability of accessing only single bit of a port.
• Here only single bit is accessed and rest are unaltered.
• SYNTAX: “SETB X. Y”.
• Here X is the port number and y is the desired bit.
• Example: SETB P1.2

Here the second bit of port 1 is set to 1.

Other than SETB ,CLR are there any single bit instructions ?

• There are total 6 single-bit instructions.
• CPL bit : complement the bit (bit= NOT bit).
• JB bit,target: Jump to target if bit equal to 1.
• JNB bit,target: Jump to target if bit is equal to 0.
• JCB bit,target: Jump to target if bit is equal to 1 and then clear bit.

Review Buck, Boost, LDO, PWM, and FIR vs IIR

Charis Poag, 1/5/13

The following information was obtained for a company I am applying for (omitted name). One of the Design directors asked me some questions during the interview. So I went ahead and did some research to refresh my mind on their technologies over the weekend.  

Power i nformation came from: http://users.ece.utexas.edu/~kwasinski/teaching.html and some from Wikipedia and youtube videos.

Main knowledge of DSP information came from: http://users.ece.utexas.edu/~bevans/courses/realtime/lectures/index.html

a) Buck converters-

A buck converter is a method to "step-down DC to DC converter".   Our goal is to have a high efficiency design, ie our lossless objective: Power in = power out, thus Vin*Iin =Vout*Iout -> Vout/Vin = Iin/Iout. The typical buck converter design is shown in the figure below.

Note: the switch is typically a MOSFET,IGBT, or BJT.

Idea: voltage regulation by the inductor--

Also energy stored in an inductor is described as-

The theory of operation is fairly simple, with an inductor and two switches (usually created with a transistor and a diode) which controls the inductor converter. The best way to understand this is to think in terms of the inductor's reluctance to allow a change in current. So when the switch is open (seen in picture below as the "off" position), the current in the circuit is 0 in the beginning. But when the switch is closed, the current begins to increase, but the inductor does not want it to change from 0, so it attempts to fight the increase by dropping the voltage. The voltage drop counters the voltage of the source and reduces the net voltage across the load. Over time, the inductor allows current to increase slowly by  decreasing the voltage it drops, thus increasing the net voltage seen by the load. This process causes the inductor to store the energy in the form of a magnetic field.

If the switch is opened before the inductor fully charges (in other words, before it has allowed all current to pass through by reducing its own voltage drop to 0), then there will always be a voltage drop across it. Thus the net voltage seen by the load is always less than the input voltage source. Overtime, the inductor allows the current to decrease gradually, which it does by decreasing the voltage across itself. During this time, the inductor is discharging its stored energy into the rest of the circuit.

If the switch is closed again before the inductor fully discharges, the load will always see a non-zero voltage. The capacitor placed in parallel with the lad helps smooth out this voltage waveform as the inductor charges and discharges each cycle. As seen in the figure below the circuit diagrams.

By keeping the inductor in a state of not fully charging and discharging we are able to create a circuit which lowers the output voltage. This also allows us to control the power efficiency of the circuit. A more in depth discussion of this circuit can be found on Wikipedia or other educational resources which describe the continuous and discontinuous modes of the inductors cycles and control of the current seen across the load. For example in continuous mode if you can find out what duty cycle you need to  step down 12v to 3v. In that particular case you need a 25% duty cycle in our theoretical ideal circuit.

This is due to D (uty cycle) =Vout/Vin =0.25 duty cycle.

http://en.wikipedia.org/wiki/Buck_converter

b) Boost converters-

 Note: the switch is typically a MOSFET,IGBT, or BJT.

Idea: voltage regulation by the inductor--

Also energy stored in an inductor is described as-

The circuit above is used to take a DC voltage and raise it to a higher DC voltage. The DC-to-DC power converter uses switched-mode power supply (SMPS) containing at least two semiconductor switches (a diode and a transistor) with at least one energy storage element, a capacitor, inductor or the two in combination. Filters made of capacitors(sometimes in combination with inductors) are normally added to the output of the converter to reduce output voltage ripple.

 This is also called a "step up converter" because it steps up the voltage source. Since power must be conserved (P=VI), the output current is lower than the source current. And as mentioned in the Buck converter, we  use the inductors capability to control the voltage, due to the rate of change of current across itself. Boost converters are often used for DC sources such as batteries, solar panels, rectifiers and DC generators.

The circuit analysis is quite similar to the buck converter. As mentioned in that section, we use the inductor to resist changes in current, thus controlling the voltage. In a boost converter, the output voltage is always higher than the input voltage.

The basic principle of the boost converter consists of two distinct states as see above:

1) The on state: the switch is closed, resulting in an increase of inductor current

2) The off state: the switch is open and the only path offered to the inductor current is through the flyback diode, the capacitor C and the load R. This results in transferring energy accumulated during the on state into the capacitor connected in parallel with the load.
 

To find out what duty cycle you need to say convert 12v to 24v then use the duty cycle conversion equation. D = 1-(12/24) = 1-0.5 = 0.5.

c) PWM-

Used for controlling power to inertial electrical devices, made practical my modern power switches. Longer the switch is on compared to off periods, the higher the power supplied to load is. PWM is use for several electronic application, including: telecommunications signal modulation,  power delivery to a load, voltage regulation, and audio effects/amplification.  An example of how PWM is used to convert digital signal to an analog signal is shown below.

Above is an example to control speed of a motor. Lets say the duty cycle = time on/time off = 0.5 voltage swings from 0 to 12 volts. Then average voltage = 0.5 * 12v = 6volt average being supplied to the motor.

**Also used for Digital to Analog converter.

From my experience , an easy way of creating a duty cycle could be done by using a microcontroller which you can turn off and on an output voltage that is  controlled with a timing interrupt. A wonderful reference for a PWM driver can be found on my professor Valvano's website (http://users.ece.utexas.edu/~valvano/EE345L/Lectures/LLec27_PWMmotor.pdf)

Example code of a timer to create PWM on an ARM processor can be found below.

Here are some examples of duty cycles:

// Timer0APWM.c

// Runs on LM3S811

// Use Timer0A in PWM mode to generate a square wave of a given

// period with 50% duty cycle.

// Daniel Valvano

// June 27, 2011

/* This example accompanies the book

   "Embedded Systems: Real Time Interfacing to the Arm Cortex M3",

   ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2011

 Copyright 2011 by Jonathan W. Valvano, valvano@mail.utexas.edu

    You may use, edit, run or distribute this file

    as long as the above copyright notice remains

 THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

 OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

 VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,

 OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 For more information about my classes, my research, and my books, see

 http://users.ece.utexas.edu/~valvano/

 */

#define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))

#define TIMER0_TAMR_R           (*((volatile unsigned long *)0x40030004))

#define TIMER0_CTL_R            (*((volatile unsigned long *)0x4003000C))

#define TIMER0_TAILR_R          (*((volatile unsigned long *)0x40030028))

#define TIMER0_TAMATCHR_R       (*((volatile unsigned long *)0x40030030))

#define TIMER0_TAMATCHR_R       (*((volatile unsigned long *)0x40030030))

#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration,

                                            // function is controlled by bits

                                            // 1:0 of GPTMTAMR and GPTMTBMR

#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode

                                            // Select

#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode

#define TIMER_CTL_TAEN          0x00000001  // GPTM TimerA Enable

#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load

                                            // Register Low

#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load

                                            // Register

#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))

#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))

#define SYSCTL_RCGC1_R          (*((volatile unsigned long *)0x400FE104))

#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))

#define SYSCTL_RCGC1_TIMER0     0x00010000  // timer 0 Clock Gating Control

#define SYSCTL_RCGC2_GPIOD      0x00000008  // port D Clock Gating Control

void WaitForInterrupt(void);  // low power mode

// period is number of clock cycles in PWM period ((1/clock) units)

void PWOut_Init1(unsigned short period){

  volatile unsigned long delay;

  SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0;// activate timer0

  SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOD; // activate port D

  delay = SYSCTL_RCGC2_R;          // allow time to finish activating

  GPIO_PORTD_DEN_R |= 0x10;        // enable digital I/O on PD4

  GPIO_PORTD_AFSEL_R |= 0x10;      // enable alt funct on PD4

  TIMER0_CTL_R &= ~TIMER_CTL_TAEN; // disable timer0A during setup

  TIMER0_CFG_R = TIMER_CFG_16_BIT; // configure for 16-bit timer mode

                                   // configure for alternate (PWM) mode

  TIMER0_TAMR_R = (TIMER_TAMR_TAAMS|TIMER_TAMR_TAMR_PERIOD);

  TIMER0_TAILR_R = period-1;       // timer start value

//  TIMER0_TAMATCHR_R = period/4;    // duty cycle = 75%

  TIMER0_TAMATCHR_R = period/2;    // duty cycle = 50%

//  TIMER0_TAMATCHR_R = 3*period/4;    // duty cycle = 25%

  TIMER0_CTL_R |= TIMER_CTL_TAEN;  // enable timer0A 16-b, PWM, 50% duty

}

//debug code

int main(void){

//  PWOut_Init1(300);                // initialize timer0A in PWM mode (20,000 Hz)

//  PWOut_Init1(1200);               // initialize timer0A in PWM mode (5,000 Hz)

  PWOut_Init1(6000);               // initialize timer0A in PWM mode (1,000 Hz)

  while(1){

    WaitForInterrupt();

  }

}

d) LDO-

http://www.analog.com/library/analogDialogue/archives/41-05/ldo.html

For the circuit above (LDO) the output voltage is defined as

A "low-dropout" regulator is used for DC voltage regulators which operate with a very small input-output differential voltage. The advantage for using a low dropout voltage is because they a lower minimum operation voltage, but higher efficiency operation and heat dissipation.

Primarily, the main components for an LDO circuit consists of a power FET and a differential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes to maintain a constant output voltage.

These LDO regulators work in the same way as all linear voltage regulators, however the main difference is their schematic topology. Instead of an emitter follower topology (shown below, low-dropout regulators use open collector or open drain topology. This allows transistor saturation, which allows the voltage drop from the unregulated voltage to the regulated voltage to be as low as the saturation voltage across the transistor.

Figure: PNP version of the emitter follower circuit

Just for my reference, I added a quick discussion of transistors. The transistor allows it to function as an amplifier or switch. This is accomplished by using a small amount of electricity to control a gate on which larger supply of electricity. The transistor's supply of voltage is comparable to turning a valve to control a supply of water. 

Transistors have 3 parts: base, collector, and emitter. The base is the gate controller for the device for larger electrical supply the emitter is the outlet for the supply. The collector is the larger electrical supply, and the emitter is the outlet for that supply. By sending varying levels of current from the base, the amount of current flowing through the gate from the collector can be regulated. In this way, a very small amount of current may be used to control a large amount of current, for example within an amplifier. The same process is used to create binary code for digital processors, but in this case a voltage threshold of 5 volts is needed to open the collector gate. This process allows the transistor to be used as a switch with binary function of - 5 volts = on and less than 5 volts = off.

e) Advantages of FIR vs IIR filters

A wealth of information on FIR filters can be found here: http://www.eas.uccs.edu/wickert/ece2610/lecture_notes/ece2610_chap5.pdf

A wealth of information on IIR filters can be found here:

http://www.eas.uccs.edu/wickert/ece2610/lecture_notes/ece2610_chap8.pdf

Quick notes about the above information:

• x[n] is the input signal,
• y[n] is the output signal,
• are the filter coefficients, also known as tap weights, that make up the impulse response,
• is the filter order; an th-order filter has (N+1) terms on the right-hand side. The x[n-i] in these terms are commonly referred to as taps, based on the structure of a tapped delay line that in many implementations or block diagrams provides the delayed inputs to the multiplication operations. One may speak of a 5th order/6-tap filter, for instance

FIR- current input depends on pas and previous input samples as well as previous output samples.

	IIR (feedback)- y[n] = b0x[n]+b1x[n-1]+...+bmx[n-m] - a1y[n-1]-a2y[n-2]-any[n-N]	FIR- y[n] = b0x[n]+b1x[n-1]+...+bmx[n-N] = sum from i= 0 to N (bi * x[n-i])
stability	Can be unstable, can have limit cycles	Liner phase always possible, no limit cycles
Order	less	more
History	Derived from analog filters	No analog history
other		Polyphase implementation possible can always be made causal.
	Use less memory and calculations than similar FIR filters	More memory
	Recursive implementations (short order)	Too long and may cause various application problems (long order)

IIR filters are difficult to control and  have no particular phase, where as FIR filters make linear phase always possible. IRR can be unstable, whereas FIR is always stable. IIR, when compared to FIR, can have limited cycles, but FIR has no limited cycles. IIR is derived from analog, where as FIR has no analog history. IIR can make polyphase implementation possible, whereas FIR can be made casual (linear time-invariant system; depends only on past and present inputs, not future).